1. Field of the Invention
The present invention relates to an apparatus comprising a clock control circuit suitable for synchronous control in a wide frequency band, a method of controlling clock signals and a device using an internal clock signal synchronized to an external clock signal.
2. Related Art Statement
Recently, a computer system sometimes adopts a clock synchronous type memory, such as a synchronous DRAM, in order to fulfill the requirements for faster processing. A synchronous type memory is designed to use a clock, which is synchronized to a clock signal controlling a memory circuit, also within the memory.
When a delay occurs between a clock signal used within the memory (hereinafter referred to as an internal clock signal) and an external clock signal, such as a clock signal to control the memory circuit, and particularly when the operating speed is high, malfunction is apt to occur in a circuit even when the delay time is small.
Accordingly, a clock control circuit is provided in a semiconductor integrated circuit to synchronize an internal clock signal to an external clock signal.
FIG. 1 is a circuit diagram showing a related art on such a clock control circuit. FIG. 2 is a waveform diagram illustrating the theory. The circuit in FIG. 1 adopts an STBD (Synchronous Traced Backwards Delay) as a clock control circuit.
In FIG. 1, an external clock signal CK, shown in FIG. 2, is inputted to an input terminal 1. The period of the external clock signal CK is supposed to be xcfx84. This external clock signal CK is taken in through a receiver 2. The receiver 2 outputs an amplified clock signal CLK after waveform shaping of the external clock signal. When a delay time at the receiver 2 is D1, the clock signal CLK outputted from the receiver 2 becomes as shown in FIG. 2. A clock control circuit 20 is designed to generate a signal delayed by two periods of the external clock signal thereto.
In order to delay the clock signal CLK by (2xcfx84xe2x88x92D1), the clock control circuit 20, first, generates a pulse FCL, which rises after the time A from the rising timing of the clock signal CLK outputted from the receiver 2 as shown in FIG. 2. The time from the rising of this pulse FCL to the next rising of the clock signal CLK is, as shown in FIG. 2, the time xcex94(=xcfx84xe2x88x92A). The clock control circuit 20 measures a time (xcfx84xe2x88x92A), and generates a next pulse RCL after the time 2(xcfx84xe2x88x92A) from the rising of the pulse FCL (see the pulse RCL in FIG. 2).
As shown in FIG. 2, the time from the rising of the pulse RCL to the rising of the next clock signal CLK is xcfx84xe2x88x92xcex94=xcfx84xe2x88x92(xcfx84xe2x88x92A)=A. Now, the time from the rising of the pulse RCL to the rising of the external clock signal CK to be inputted next is supposed to be D2. When D2 is a time as shown in FIG. 2, an internal clock CKxe2x80x2 (FIG. 2) is generated synchronizing to the external clock CK by being delayed by 2 periods to it.
As shown in FIG. 2 D2 is satisfactory so long as it is a value between D1 and A and has a relation of (D2+D1)=A. That is, when the time D2 is a delay time in an outputting stage, it means that an internal clock signal synchronized to the external clock signal can be generated by providing a delay circuit, which operates with the delay time A, the sum of the delay time D1 due to the receiver 2 and the delay time D2 in the outputting stage, and providing another delay circuit having a delay time of the time 2(xcfx84xe2x88x92A).
Next, the operation of a circuit according to a related art will be described with reference to a block diagram shown in FIG. 1, waveform diagrams in FIGS. 7 and 8, and explanatory views shown in FIGS. 9 to 12. Particularly, the operation characteristics of an STBD to store the propagation condition of forward pulse and to control the propagation of rearward pulse corresponding to the stored data is described in detail.
The external clock signal CK having a period xcfx84 as shown in FIG. 7 is inputted to a receiver 2 via an input terminal 1, and CLK shown in FIG. 7 is outputted from the receiver 2. When a delay of the receiver 2 is D1, CLK is delayed by D1 to CK. When no clock control circuit is used, this delay D1 becomes, as it is, skew of the external clock signal and the internal clock signal. The more the external clock signal becomes high frequency and xcfx84 becomes smaller, the more the effect of this skew becomes great. The output signal CLK of the receiver 2 is inputted to an inverter 10, a control pulse generating circuit 9 and a delay monitor 3. At the control pulse generating circuit 9, the control pulse P as shown in FIG. 7 is generated. In a clock control circuit using an STBD, it is required to initialize all forward-pulse delay circuits before forward pulse FCL is inputted to the first delay unit. By reason of this, a control pulse P having a width narrower than the delay time A of a delay monitor 3 is generated, and control is carried out using this control pulse P. The output signal FCL of the delay monitor 3 is delayed by A to CLK and inputted to a first forward-pulse delay circuit 5-1 of a forward-pulse delay line 5.
The N-th forward-pulse delay circuit forming a forward-pulse delay line outputs a logical value, which is similar to the output of the (Nxe2x88x921)th forward-pulse delay circuit, to the (N+1)th forward-pulse delay circuit when the control pulse P is xe2x80x9cLxe2x80x9d and outputs xe2x80x9cLxe2x80x9d to initialize a forward-pulse delay line 5 when P is xe2x80x9cHxe2x80x9d.
Output signals of forward-pulse delay circuits are also inputted to state-holding circuits. One of output signals of rearward-pulse delay circuits is also inputted to state-holding circuits. State-holding circuits have two states to take corresponding to signals inputted. The state-holding circuit takes the set state when P is xe2x80x9cLxe2x80x9d and forward pulse is propagated by the corresponding forward-pulse delay circuit. When P is xe2x80x9cHxe2x80x9d and rearward pulse is propagated by the corresponding rearward-pulse delay circuit, the state-holding circuit takes the reset state.
An output signal of the state-holding circuit is inputted to a rearward-pulse delay circuit. When the state-holding circuit to which the rearward-pulse delay circuit is connected is in the set state, the N-th rearward-pulse delay circuit inputs a logical value, which is similar to the output of the (N+1)th rearward-pulse delay circuit, to the (Nxe2x88x921)th rearward-pulse delay circuit. When the state-holding circuit connected to the rearward-pulse delay circuit is in the reset state, it outputs a logical value similar to the output of the receiver.
Next, the operation from the input of the forward pulse FCL to a forward-pulse delay line to the output of the output signal RCL from a rearward-pulse delay line is described in detail with reference to FIGS. 8 and 9 to 12. Each of FIGS. 9 to 12 shows the state of t0 to t3 in FIG. 8. Suppose that the delay time of a delay circuit is xcex94du clock period is 10xcex94du, the pulse width is 5xcex94du, the width Axe2x80x2 of the control pulse P is 2xcex94du, the delay time A of the delay monitor is 3xcex94du. The set state is expressed with S and the reset state is expressed with R. The numerals marked on delay lines express the output of a delay circuit; xe2x80x9c1xe2x80x9d (=xe2x80x9cHxe2x80x9d) and xe2x80x9c0xe2x80x9d (=xe2x80x9cLxe2x80x9d) (xcex94du expresses a delay time per stage of delay circuits).
Now, suppose that, in the initial state at time to, all state-holding circuits are in the reset state R. At this time, as an external clock signal has not been inputted, the output state of all forward-pulse delay circuits and rearward-pulse delay circuits is at xe2x80x9cLxe2x80x9d (FIG. 9).
When the forward pulse FCL is inputted to forward-pulse delay circuits, the forward pulse is then propagated by the forward-pulse delay line until the control pulse becomes xe2x80x9cHxe2x80x9d. As shown in FIG. 10, at time t1, when the forward pulse F1 has been propagated up to the 7th stage and the propagation is stopped due to P""s becoming xe2x80x9cHxe2x80x9d and then, the state-holding circuits in the first stage up to the 7th stage turn to the set state S, and the state-holding circuits in the 8th stage up to the last stage remain in the reset state R. At this time, CLK (=xe2x80x9cHxe2x80x9d) is inputted to the rearward-pulse delay circuit in the 7th stage to the last state, and the rising of rearward pulse is formed. On the other hand, as P is xe2x80x9cHxe2x80x9d the output of forward-pulse delay circuits becomes xe2x80x9cLxe2x80x9d and then the forward pulse F1 disappears after that.
At time t2, as P remains at xe2x80x9cHxe2x80x9d the rising of rearward pulse R1 is propagated to the preceding stage, changing state-holding circuits to the double-stage (=Axe2x80x2/xcex94du) reset state R (FIG. 11). This is for the purpose of generating rearward pulse from the stage where forward pulse is stopped even when forward pulse is not propagated up to the 7th stage because the period xcfx84 is shortened due to jitter.
Finally, when the input signal CLK for rearward-pulse delay lines becomes xe2x80x9cLxe2x80x9d at time t3, in the stages of state-holding circuits in the reset state, namely, in and after the 6th stage, the output of rearward-pulse delay circuits changes to xe2x80x9cLxe2x80x9d and the falling of rearward pulse is formed (FIG. 12).
Attention is required to a fact that the pulse width of rearward pulse becomes narrow by the number of stages of state-holding circuits which have been reset as an anti-jitter measure. After this, by repeating the operation in FIGS. 9 to 12, a signal RCL being delayed by xcfx84xe2x88x92A from the rising of the output signal CLK of a receiver can be outputted.
The output signal RCL of rearward-pulse delay lines is inputted to an output buffer 8 and outputted as an internal clock signal CKxe2x80x2 after being delayed by D2 to the rearward pulse RCL.
The delay time xcex94 total of the internal clock signal CKxe2x80x2 to the external clock signal CK is:
xcex94total=D1+A+2(xcfx84xe2x88x92A)+D2
When the delay time of the receiver 2 and the output buffer 8 is known and A=D1+D2, the following equation holds good:                               Δ          ⁢                      xe2x80x83                    ⁢          total                =                  D1          +          A          +                      2            ⁢                          (                              τ                -                A                            )                                +          D2                                        =                  D1          +                      (                          D1              +              D2                        )                    +                      2            ⁢                          (                              τ                -                                  (                                      D1                    +                    D2                                    )                                            )                                +          D2                                        =                              2            ⁢                          (                              D1                +                D2                            )                                +                      2            ⁢            τ                    -                      2            ⁢                          (                              D1                +                D2                            )                                                              =                  2          ⁢          τ                    
As xcex94 total becomes 2xcfx84, consequently, the external clock signal and the internal clock signal are synchronized.
FIG. 13 shows the state of the state-holding circuit 6 when propagation of forward pulse was stopped by the control pulse P In this figure, S represents the set state and R represents the reset state respectively.
As shown in FIG. 13, as the state-holding circuits 6-(N+1) to 6-L after the N-th stage, where forward pulse FCL was propagated, are in the reset state, to rearward-pulse delay circuits corresponding to these state-holding circuits 7-(N+1) to 7-L are ready to have the clock signal CLK inputted, and electric power is consumed.
In consequence, the circuit in FIG. 1 has a problem that, electric power even in stages where forward pulse FCL is not propagated.
As application is widened when the operating frequency band of a clock control circuit is wide, and as the operation tests on clock control circuits are carried out in a low-frequency band, it is required to widen the respondent operating frequency band in low frequency. When an external clock signal becomes low frequency, its period xcfx84 becomes longer and forward pulse is propagated in a relatively large number of stages. Accordingly, in order to widen the operating frequency band in low frequency, the number of stages of delay lines should be increased so that forward pulse does not reach the end of a delay line.
Actually, however, as the operation is mainly done in high frequency, more electric power is consumed in the part where forward pulse is not propagated during the operation in high frequency than in stages where forward pulse was propagated.
Thus, aforesaid clock control circuit according to a related art has a problem that, during the operation in high frequency, electric power is mostly consumed by delay units in stages where forward pulse is not propagated than by delay units in stages where forward pulse was propagated.
An object of the present invention is to provide an apparatus comprising a clock control circuit, which is able to reduce electric power consumption during the operation time in high frequency, a method of controlling clock signals and a device using an internal clock signal synchronized to an external clock signal.
A clock control circuit according to the present invention comprises a forward-pulse delay line which is configured by cascading a plurality of stages of forward-pulse delay circuits to delay inputted signals by propagating said inputted signals with a predetermined delay time, and delays forward pulse by propagating said forward pulse, a rearward-pulse delay line which is configured by cascading a plurality of stages of rearward-pulse delay circuits to delay inputted signals by propagating said inputted signals with a predetermined delay time, and delays rearward pulse by propagating said rearward pulse, a control device to propagate said rearward pulse by said rearward-pulse delay lines in a number of stages corresponding to the number of stages where said forward pulse was propagated by said forward-pulse delay lines, a forward-pulse detecting device to detect whether said forward pulse was propagated or not in one or a plurality of predetermined stages, and an electric power consumption control device to control electric power consumption of at least rearward-pulse delay circuits out of said forward-pulse delay circuits, said rearward-pulse delay circuits and said control device, corresponding to the detected result of said forward-pulse detecting device.
A method of controlling clock signals according to the present invention comprises a procedure to detect stages, where said forward pulse was propagated, in order to control electric power consumption of state-holding circuits, which output state signals to propagate rearward pulse by said rearward-pulse delay circuits in a number of stages corresponding to the number of stages of forward pulse which was propagated by forward-pulse delay circuits to delay inputted signals by propagating them with a predetermined delay time, rearward-pulse delay circuits to delay inputted signals by propagating said inputted signals with a predetermined delay time and said forward-pulse delay circuits, and a procedure to control electric power consumption of at least said rearward-pulse delay circuits out of said forward-pulse delay circuits. rearward-pulse delay circuits and state-holding circuits corresponding to this detected result.
Other features and advantages of the present invention will become apparent enough from the following description.